US05381143Digital signal coding/decoding apparatus, digital signal coding apparatus, and digital signal decoding apparatus
AssigneeSony Corporation
Assign./FiledJan. 10, 1995/ Sept. 8, 1993
InventorsShimoyoshi; Osamu, Akagiri; Kenzo, Abe; Miki, Watanabe; Takahiro
SummaryEnhancement to ATRAC. Detailed description of ATRAC's Block Floating operations. Some commonality with US05301205.
AbstractA digital signal processing system comprising a compressor, an expander and a scale-down circuit. The compressor includes non-block frequency analyzer that frequency analyzes the digital input digital signal, without dividing it into block, to provide a frequency range signal in each of plural frequency ranges. A block frequency analyzer divides the frequency range signals into blocks and performs a block frequency analysis of each block of the frequency range signals to provide a block of spectral coefficients. A quantizer quantizes the block of spectral coefficients from the block frequency analyzer to provide a block of a compressed signal. The expander includes a block frequency synthesizer that performs a block frequency synthesis to transform, from the frequency domain to the time domain, the spectral coefficients in each of the frequency ranges in each block of the compressed signal to provide, in each of the frequency ranges, a block of a reproduced frequency range signal. A non-block frequency synthesizer synthesizes the reproduced frequency range signals, without dividing them into blocks, to provide the digital output signal. Finally, the system includes a scale-down circuit that scales down values in the block frequency analysis performed by the block frequency analyzer or the block frequency synthesis performed by the block frequency synthesizer. The scale-down circuit operates to cause the noise levels resulting from scaling down the values to be different in each of the frequency ranges.